1. Field of the Invention
The present invention relates generally to data transfers in systems, and in particular, relates to improving data transfer and bus efficiency by minimizing bus contention when a device reads data from memory.
2. Background Information
In computer systems, components are coupled to each other via one or more busses. A variety of components can be coupled to the bus, thereby providing intercommunication between all of the various components/devices. An example of a bus that is used for data transfer with a processor or for data transfer between a memory and another device is the peripheral component interconnect (PCI) bus.
In order to relieve a processor of the burden of controlling the movement of blocks of data inside of a computer, direct memory access (DMA) transfers are commonly used. With DMA transfers, data can be transferred from one memory location to another memory location, or from a memory location to an input/output (I/O) device (and vice versa), without having to go through the processor. Additional bus efficiency is achieved by allowing some of the devices connected to the PCI bus to be DMA masters.
When transferring data using DMA methods, scatter gather descriptors are often used. High performance I/O controllers, such as gigabit Ethernet media access control (MAC) network controllers, are typically scatter gather descriptor-based bus-mastering devices that allow a computer to communicate with a network. The scatter gather descriptors are used to provide address and control information about data buffers (or xe2x80x9cscatter gather elementsxe2x80x9d) in memory that the controller needs to read or write for I/O operations. For example, the descriptors provide information such as the memory location from where bytes of data are to be moved, the address to where the bytes should go, the number of bytes to move, etc.
To read a data buffer of a memory using DMA transfers, such as when the data has to be retrieved from memory so that the data can be transmitted by the controller, a driver for the controller first obtains the data buffer""s physical address and length, and places this information and other control information into descriptor(s). Next, the driver writes to a command register of the controller to inform the controller that the descriptor(s) are ready to be processed. The controller then DMA transfers the descriptor(s) from memory to a first-in-first-out (FIFO) buffer, for example, so that the controller can obtain the data buffer""s information (e.g., identify the data buffer""s memory location, length, etc.). After the controller has processed the descriptor(s) to obtain this information, the controller DMA transfers the contents/data (e.g., frames) from the data buffer referred to by the descriptor(s).
After the DMA transfer from the data buffer is completed or after the frame has been sent, the controller informs the driver that the xe2x80x9csendxe2x80x9d or the xe2x80x9creadxe2x80x9d is complete. Indication of this completion is typically required, so that the driver can allow the frame""s data to be swapped out of the data buffer (e.g., out of physical memory) by a memory manager. The controller informs the driver of these completions generally by writing to a status field of the frame""s descriptor.
Each of these writes by the controller uses bus bandwidth. As more frames are sent to the controller, more of these completion writes occur. Since no actual frame data is being transferred during these completion writes, such writes are overhead.
With high-speed networks such as gigabit Ethernet, the PCI bus can be a throughput bottleneck. At gigabit Ethernet speeds, over 81 thousand maximum-sized frames can be sent per second, and over 1.6 million minimum-sized frames can be sent per second. At these frame rates, completion writes can add up to a significant amount of overhead. Such overhead reduces bus and data transfer efficiency, and can cause performance penalties.